Sr. Engineer, Verifications

Description

The company makes precision timing products, using MEMS technology in place of quartz devices.

MEMS timing parts are already used in more than 400 applications, including AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

More than 4 billion devices have shipped.

You will join a team designing MEMS timing ICs. You do not need to meet every requirement below to be considered.

Responsibilities

• Build SV-RNM models for analog and mixed-signal circuits.
• Write the verification plan from chip or block specifications.
• Build UVM verification environments with scoreboards, monitors and sequencers.
• Verify digital top-level designs in SystemVerilog.
• Define and write SystemVerilog Assertions.
• Define functional coverage and write covergroups.
• Run simulations and debug the results.
• Review verification results to sign off tape-out.
• Share information and ideas with design, test and verification colleagues.

Requirements

• Master's degree in electrical or computer engineering or a related field with 5 years of semiconductor verification experience, or a bachelor's degree with 8 years.
• Strong spoken and written English.
• Proficient in SystemVerilog, including object-oriented programming.
• Fluent in scripting with Perl or Python.
• Proficient in UVM, gained through work experience.
• Strong experience writing SystemVerilog Assertions.
• Understanding of analog schematics and experience with Cadence Virtuoso.
• Basic understanding of digital design in Verilog.
• Able to work effectively with geographically spread mixed-signal, digital and analog design engineers.
• Able to work independently and solve hard problems.
• Desired: experience generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS) or similar techniques.
• Desired: experience with the UVM-AMS methodology.
• Desired: solid experience with Formal Property Verification.
• Desired: C++ object-oriented programming.
• Desired: excellent written and verbal English.
• Desired: experience with analog mixed-signal verification.
• Desired: a record of working well with others in a fast-paced, collaborative setting.
• Desired: knowledge of analog design.
• Desired: knowledge of synthesizable digital design.
• Desired: experience verifying datapath designs, including filters.

Conditions

The company is an equal opportunity employer. Decisions are based on qualifications, merit and business needs, without discrimination on any legally protected basis.

Benefits

• Quarterly bonus on top of base salary, tied to achieving innovation goals.
• Equity grants in the company.