Senior CAD Engineer – Physical Verification

Description

The company makes memory and storage products.

This full-time role focuses on physical verification for memory chip designs, working across process, design, layout, modeling and verification groups.

Responsibilities

• You will build and maintain verification tools, flows and methods for DRAM, HBM, NAND and newer memory designs.
• You will write, debug, qualify and release Calibre DRC and LVS rule decks in SVRF.
• You will turn process design rules into checks, and set the test cases, coverage goals and regression methods that prove them.
• You will work with other groups to set signoff plans and fix verification problems.
• You will advise design teams on methods, waivers and debugging, and deliver training, documentation and production support.
• You will assess EDA tools that improve verification quality, speed and capacity.
• You will automate setup, runs and reports, including AI-assisted analysis and debugging.
• You will lead technical projects and help shape the physical verification roadmap.

Requirements

• A bachelor's or master's degree in electrical engineering, computer engineering or computer science, or equivalent.
• 5+ years of industry experience in CAD, EDA or semiconductor design.
• Hands-on experience with DRC and LVS physical verification, IC layout and process design rules.
• You can read design-rule requirements and resolve complex verification issues in production flows.
• Python plus at least one other language such as SKILL, Tcl, Perl, C or C++, along with Linux/Unix and shell scripting.
• Solid CMOS and VLSI fundamentals, clear communication and practical debugging skills across global teams.
• Preferred: experience building and qualifying Calibre DRC and LVS rule decks in SVRF with nmDRC, nmLVS and RVE.
• Preferred: knowledge of layout-dependent effects, ERC, PERC, antenna and density checks.
• Preferred: experience optimizing rule-deck coverage, runtime and memory use.
• Preferred: experience with Cadence Virtuoso, SKILL or Cadence physical verification tools.
• Preferred: experience applying AI/ML, large language models or agentic AI to engineering workflows.
• Preferred: experience with source control, automated testing and release management.
• Preferred: knowledge of DRAM, HBM, NAND or emerging memory development.

Conditions

The US base salary range is $104,000.00 - $221,000.00 a year.

This range covers base pay only, not bonus, equity or benefits.

Pay is set by role, level and location, and within the range depends on factors such as knowledge, skills, experience, tenure and education.

The pay scale may change with business needs, and a recruiter can share the range for your preferred location.

The posting includes a link with information on the right to work.

The company does not use child labor and never charges candidates recruitment fees.

Benefits

• Medical, dental and vision plans are offered in all locations.
• Income protection if you cannot work due to illness or injury, and paid family leave.
• A paid time-off program and paid holidays.
• A benefits guide is available on the careers site.
• Bonuses and equity may be offered in addition to base pay.