Sr. Staff Engineer, IP Runtime

Description

The company builds AI hardware and software, and has developed a high performance RISC-V CPU in-house. The team is growing and is hiring engineers at a range of seniority levels.

This role sits at the boundary between hardware and software. You will decide how hardware blocks are initialized, coordinated, and used by the runtime, including how workloads are dispatched, scheduled, synchronized, and run on the accelerator. You will also solve performance problems through implementation, bring-up, and debugging.

The role is hybrid, based in Toronto, ON or Austin, TX.

Candidates are assessed for the level that fits them during interviews, and the offer will match that level, which may differ from the level in this posting.

Responsibilities

• Define the architecture and implementation of the runtime that controls execution, scheduling, synchronization, and resource management across the company's custom processor, accelerator, memory, and data-movement IP.
• Build low-level runtime components that bring up hardware IP, send work to processor and accelerator engines, track dependencies, and manage resources efficiently.
• Design runtime interfaces and data-movement paths that keep memory access, synchronization, and execution efficient and predictable.
• Find bottlenecks across the runtime and the hardware/software stack, and drive gains in latency, throughput, scalability, and reliability.
• Shape the direction of the runtime stack, work directly with customers and field-facing teams, and turn real workload needs into runtime changes. Stay hands-on with design, coding, performance analysis, bring-up, and debugging.

Requirements

• Expert in C or C++, with a record of designing and shipping complex, performance-critical systems.
• Hands-on experience close to the hardware in low-level, embedded, bare-metal, or accelerator environments, turning hardware specifications into reliable software behavior.
• Strong grasp of runtime fundamentals: command execution, scheduling, synchronization, memory movement, resource management, and parallelism.
• Skilled at debugging and optimizing systems end to end, particularly at the hardware/software boundary.
• Technical leader who works well across hardware, firmware, compiler, and systems teams and mentors other engineers.

Conditions

Hybrid work, based in Toronto, ON or Austin, TX.

This offer requires that you be eligible to access U.S. export-controlled technology under U.S. export laws, including the Export Administration Regulations (EAR), which cover transfers to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2) and apply both inside and outside the U.S. Depending on your citizenship or permanent residency status, or on whether a license from the U.S. Commerce Department or another federal agency can be obtained, the offer may be conditional. If U.S. export laws make employment impossible, the offer will be withdrawn.

The company is an equal opportunity employer.

Benefits

• Competitive compensation and benefits package.
• Base and variable compensation targets for all engineers range from $100k to $500k. Experience, skills, education, background, and location all affect the final offer.