Datacenter & Agentic AI Workload Performance Analysis Engineer

Description

The company is working on advanced AI technology and builds the software, compilers, platforms, networking and semiconductors that go with it, aiming for better performance, easier use and lower cost.

The team has designed a high-performance RISC-V CPU from scratch and is growing, with openings for contributors at every seniority level.

The role sits between hardware and software, focused on how real datacenter and agentic AI workloads run on next-generation RISC-V CPUs.

You would learn how real workloads shape microarchitecture decisions, how workload analysis and performance modeling connect to CPU design, RTL, emulation and silicon, how hardware and software co-design lifts throughput, scalability and performance per watt, how to reduce production workloads into representative traces for architecture exploration, and how RISC-V extensions, cloud infrastructure, compiler technology and AI software stacks are changing high-performance computing.

Responsibilities

• Bring real applications onto RISC-V platforms, characterize how they behave, and use the results to find ways to improve CPU performance, efficiency and scalability.
• Work with CPU architects, RTL designers, software engineers and compiler teams to see how heavy workloads stress the CPU, and turn those findings into architectural changes.
• Reduce large production workloads into forms usable for performance modeling.
• Check simulation results against real hardware behavior.

Requirements

• Strong background in CPU performance analysis, workload characterization or computer architecture, with experience linking software behavior to hardware performance.
• Solid grasp of modern CPU microarchitecture, including superscalar pipelines, speculative execution, memory hierarchies and vector or SIMD designs.
• Enjoy digging into complex workloads and using profiling and simulation data to locate bottlenecks and propose concrete fixes.
• Comfortable moving between hardware and software, from microarchitecture and RTL up through operating systems, compilers, runtimes and applications.
• Clear technical communicator who works well with architects, designers and software engineers on hard performance problems.
• PhD in computer engineering, electrical engineering, computer science or a related field, with strong research or industry experience in workload characterization, benchmark development, performance analysis or simulation.
• Deep knowledge of CPU architecture and RISC-V, including pipelines, speculative execution, vector or SIMD extensions, memory hierarchies and performance tradeoffs.
• Hands-on use of performance analysis and simulation tools such as Linux perf, strace, QEMU or CPU microarchitecture simulators.
• Strong programming in C, C++, Python, Bash or shell, and assembly or intrinsics, with experience close to the hardware and software boundary.
• Strong understanding of systems software, including operating systems, virtualization, compilers, runtimes and GNU or RISC-V software ecosystems.

Conditions

The role is fully remote and based in North America.

Interviews assess candidates for a suitable level, and offers match that level, which may differ from the level in this posting.

Pay ranges from $100k to $500k, including base salary and variable compensation targets, and the final offer depends on experience, skills, education, background and location.

The offer depends on your eligibility to access U.S. export-controlled technology under the U.S. Export Administration Regulations, including EAR Country Groups D:1, E1 and E2. Depending on your citizenship or permanent residency, or on obtaining a license from the U.S. Commerce Department or another federal agency, the offer may be conditional. If employment is not possible under these export laws, the offer will be withdrawn.

The company is an equal opportunity employer.

Benefits

• Highly competitive compensation package and benefits.