Senior CAD Engineer – Physical Verification

Description

The company makes memory and storage solutions, and the team builds the physical verification tools and flows that check those chips before release across DRAM, HBM, NAND and newer memory products.

Responsibilities

• Build and upkeep verification tools, flows and methods for DRAM, HBM, NAND and new memory parts.
• Write, debug, qualify and release Calibre DRC and LVS rule decks in SVRF.
• Turn process design rules into checks, and set the test cases, coverage goals and regression approaches that qualify them.
• Work with process, design, layout, modeling and verification groups to set signoff plans and fix verification problems.
• Advise design teams on methods, waivers and debugging, and deliver training, documentation and production support.
• Assess EDA tools for gains in verification quality, speed and capacity.
• Automate setup, runs and reporting, including AI-assisted analysis and debugging.
• Lead technical projects and help shape the physical verification roadmap.

Requirements

• Bachelor's or Master's degree in electrical engineering, computer engineering or computer science, or an equivalent.
• 5+ years in CAD, EDA or semiconductor design.
• Hands-on work with DRC and LVS verification, IC layout and process design rules.
• Skill in reading design-rule requirements and solving hard verification issues in production flows.
• Python plus at least one more language such as SKILL, Tcl, Perl, C or C++, along with Linux/Unix and shell scripting.
• Solid grounding in CMOS and VLSI, clear communication, and practical debugging across global teams.
• Preferred: Experience building and qualifying Calibre DRC and LVS decks in SVRF with nmDRC, nmLVS and RVE.
• Preferred: Knowledge of layout-dependent effects, ERC, PERC, antenna and density checks.
• Preferred: Experience tuning rule-deck coverage, runtime and memory use.
• Preferred: Experience with Cadence Virtuoso, SKILL or Cadence physical verification tools.
• Preferred: Experience applying AI/ML, large language models or agentic AI to engineering work.
• Preferred: Experience with source control, automated testing and release management.
• Preferred: Knowledge of DRAM, HBM, NAND or emerging memory development.

Conditions

The company shares information on your right to work.

The company does not charge candidates recruitment fees and complies with applicable labor laws.

Benefits

• Medical, dental and vision plans available in all locations, so you can pick the coverage that fits your family and budget.
• Income protection if you cannot work due to illness or injury, plus paid family leave.
• Paid time off and paid holidays.
• A benefits guide with full details is available.