LTD RET Software/Research Engineer

Description

Job Details:

This position is in the Logic Technology Development (LTD) team, working in one of the most advanced semiconductor development facilities in the world.

The LTD Resolution Enhancement Technology (RET) team is extending the limits of feature sizes that are patternable on Intel's devices, using current and future lithography manufacturing tooling. The team works closely with fab integrated lithography process and mask manufacturing teams using computational lithography tooling to optimize mask patterns and maximize manufacturing process capability. The RET team also works closely with the design rule definition teams, using lithography and patterning simulation capabilities to determine design rules for future Intel process nodes.

Responsibilities

• Optical Proximity Correction (OPC) algorithms
• Development, and implementation of Resolution Enhancement Techniques (RET) for existing and novel process technologies
• Define and selects new approaches and implementation of RET
• OPC recipe code optimization and validation
• Algorithmic design pattern layout manipulation
• Use predictive modeling, statistics, machine learning, and other data analysis techniques to collect, explore, visualize fab process data, and develop RET software algorithms and applications to compensate for physical effects in photolithography imaging and the etch pattern transfer process
• Support of production mask tapeout and RET validation
• Maintain a deep knowledge of state-of-the-art principles and trends in RET and semiconductor technology
• Creation of technical documentation and presentations

Requirements

• Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
• Minimum Qualifications:
• Bachelor's degree in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 6+ years of professional experience in the semiconductor industry
• OR
• Master's degree in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 4+ years of professional experience in the semiconductor industry
• OR
• Ph.D. in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 2+ years of professional experience in the semiconductor industry
• Hands-on professional experience includes one or more of the following:
• Pattern synthesis and mask layout manipulation
• Knowledge of OPC concepts and capabilities
• Preferred Qualifications:
• Understanding of the latest techniques for developing and optimizing OPC rule-based synthesis solutions to support both high volume and newly developing technology nodes
• For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (United States of America)
• Primary Location:
• US, Oregon, Hillsboro
• Additional Locations:
• Posting Statement:
• Position of Trust
• N/A

Benefits

• We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that make the world a better place.
• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .
• Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD
• The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
• Work Model for this Role
• This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.