Sr. Compiler Engineer

Description

The company builds high-performance, low-power generative AI inference systems, combining custom silicon, hardware and software for hyperscaler and neocloud data center customers.

It is a well funded startup with headquarters in Sunnyvale, CA and Munich, Germany, and team members work remotely across North America and Europe.

The compiler largely determines whether the inference chips reach 30% utilization or 90% and above, and you would own the backend that maps AI workloads to microcode for the current hardware and the chips that follow.

This is a clean-slate compiler project for an unusual architecture, and you would work on foundational parts of the compiler.

Agents will increasingly map and optimize models alongside engineers, so the compiler must support both, with transparent cost models, structured feedback, machine-readable diagnostics and fast iteration loops. Few teams are building for this yet.

Responsibilities

• Work on the full backend, from lowering through instruction scheduling, register and resource allocation to microcode generation.
• Manage the memory hierarchy, including SRAM residency, HBM traffic, DMA orchestration, data layout, rematerialization and data movement, so the hardware stays compute-bound instead of waiting on memory.
• Build tiling, fusion and software-pipelining strategies that narrow the gap between theoretical and achieved throughput.
• Design compiler interfaces for agents and engineers alike: structured IR access, machine-readable diagnostics, searchable tuning spaces and performance feedback you can act on.
• Handle dynamic shapes, compile latency, KV-cache management, and the different goals of time-to-first-token (TTFT) and steady-state throughput.
• Create cost models that forecast performance on silicon that does not exist yet, and keep calibrating them against real hardware.
• Pass compiler findings back into ISA and microarchitecture requirements for future silicon.

Requirements

• Hands-on production experience in code generation, optimization or graph mapping. Describe what you shipped and what it achieved.
• Experience with MLIR and/or LLVM, with meaningful contributions to an active compiler stack such as LLVM, MLIR, TVM, IREE, XLA, Triton or Inductor, or to an equivalent internal system.
• Strong modern C++ and a disciplined approach to testing and correctness. Rust: a plus.
• Experience targeting custom accelerators or non-standard ISAs. You can read a microarchitecture specification, judge its consequences, and push back on its assumptions when the compiler shows they fail.
• Strong performance intuition across the memory hierarchy, data movement, parallelism, synchronization and occupancy, and the factors that turn theoretical throughput into real throughput.
• A co-design mindset. You treat compiler, kernels, runtime, ISA and silicon as one system and work across those boundaries when that is where the performance gains are.
• Stands out: well-argued views on what current ML compilers get wrong, backed by evidence.
• Stands out: work on autotuning, auto-scheduling or polyhedral compilation.
• Stands out: serious hands-on use of agents in compiler, kernel-generation or optimization loops.
• Stands out: CUDA or Triton expertise, especially with CUTLASS or NCCL.
• Stands out: experience with VLIW, systolic, dataflow or other unconventional architectures.
• Stands out: open-source compiler contributions the team can read and discuss.

Conditions

Headquarters are in Sunnyvale, CA and Munich, Germany, and the team also works remotely across North America and Europe.

Equal opportunity and legal details are not stated in the posting.

Benefits

• Comprehensive benefits.
• Competitive compensation.
• Flexible spending options.
• Recognition programs.