Software R&D Engineer, RTL Optimization Tools

Description

The team builds in-house EDA tools in C++ that combine parallel computing, machine learning and new algorithms, alongside external EDA software.

The focus is large-scale RTL quality, timing and power optimization. This work usually mixes graph algorithms, AI and feedback from RTL designers, so experience in any of those areas is a strong fit.

Solid knowledge of DFT, clock distribution, power gating and other SOC integration topics is essential, since the techniques draw on many related fields.

The company is a leading hardware maker, so you work mainly on the latest process nodes and advanced designs rather than legacy support or niche projects. Developers have wide freedom to explore and to work across many technical areas, and you see your results in leading AI hardware.

The team is growing and is hiring an engineer for an existing opening.

Responsibilities

• Create new methods for parallel, graph-based RTL traversal, analysis and modification.
• Build strategies to quickly assess how RTL changes affect data path latency, power, DFT, clocking and power delivery.
• Investigate LLMs, GNNs, GANs and reinforcement learning to recommend or automatically make RTL changes.
• Research fast algorithms for clustering, min-cost tree covering (technology mapping), datapath implementation and other logic synthesis tasks, especially ones that make good use of human expertise.
• Own the full cycle from finding optimization opportunities to inventing, coding and deploying solutions, working directly with design teams.
• Take a broad view of your work and drive the roadmap for better hardware design productivity, not just respond to user requests.
• Write a good amount of code as part of a software engineering team.

Requirements

• An MS or PhD in Electrical Engineering or Computer Science, or equivalent experience.
• 3+ years of experience in CAD software and VLSI hardware design.
• Proven C++ development skills, especially in algorithms for graph traversal, pattern matching and optimization.
• Familiarity with RTL design in Verilog and SystemVerilog, plus hardware concerns such as scan chain insertion, MBIST, clock and power distribution and bus architectures.
• Familiarity with EDA techniques including logic synthesis, global route, static timing analysis and SAT solvers.
• Strong communication and interpersonal skills.
• Nice to have: experience with common EDA building blocks such as Verific for Verilog parsing, Espresso for logic minimization, and components for logic rewriting, tree coverage, SAT solving and combinatorial optimization.
• Nice to have: experience in high performance software, including multithreading, distributed computing and efficient memory and I/O use.
• Nice to have: software and hardware work experience, especially in SOC/IP integration or RTL design.
• Nice to have: experience with machine learning techniques for analysis, optimization and code generation.

Conditions

Hybrid work arrangement.

Base salary is set by location, experience and other objective job-related factors, within a range of 136,000 USD to 218,500 USD.

Applications are accepted until at least November 3, 2026.

The company uses AI tools in parts of its recruiting process.

The company is an equal opportunity employer and does not discriminate on protected characteristics.