Senior Embedded SW/Firmware Design Engineer

Description

The company builds defense systems that sense and detect threats, powered by Coherent Distributed Networks (CDN). It was founded in 2022 by former U.S. military veterans and Silicon Valley engineers and serves warfighters, commercial air operators, and border protection teams.

The company has raised $1B from investors including 8VC, Accel, and NEA. It has 500 employees, and the number is growing, across 5 offices: Los Angeles (headquarters), Washington, D.C., San Francisco, Seattle, and London.

The role supports R&D and product engineering, starting with next-generation radar products. You will work on several capabilities across the product line and can build skills across the product families.

Responsibilities

• Design and implement complex FPGA logic for next-generation sensor products.
• Help integrate FPGA designs with complex software systems.
• Support FPGA capabilities already deployed with U.S. and international customers.

Requirements

• Bachelor's degree or higher in computer engineering, electrical engineering, computer science, or a related field.
• 5+ years of professional experience doing detailed digital RTL design for FPGAs.
• Deep experience across the full FPGA lifecycle: RTL design, behavioral simulation, place and route, timing analysis, and hardware integration.
• Deep experience writing Verilog and SystemVerilog.
• Deep experience with ARM AMBA AXI, including AXI4, AXI4-Lite, and AXI4-Stream.
• Deep experience with AMD (Xilinx) Vivado Design Suite and SoC FPGAs such as Zynq, Ultrascale/Ultrascale+, and Versal.
• Experience with network protocols: TCP, UDP, and IP.
• Experience with serial protocols: I2C, JTAG, UART, SPI, and CAN.
• Experience using Bash and Python for scripting and testing.
• Experience changing software drivers and applications to validate FPGA designs.
• Experience with Agile processes, including Scrum, continuous integration, and test-driven development.
• Able to work with minimal supervision and collaborate in small teams.
• U.S. Person status required, because the role needs access to U.S.-only data systems.
• Preferred: experience building and implementing high-performance baseband signal processing in FPGAs.
• Preferred: experience turning high-level algorithms from Simulink, MATLAB, or similar tools into RTL, including FPGA vendor IP.
• Preferred: experience writing software drivers in C, C++, or Python to interface with FPGA designs.
• Preferred: experience with FPGA Ethernet IP blocks at 1G, 10G, 40G, or 100G.
• Preferred: experience with software-defined radios such as Ettus, NI, or HackRF.
• Preferred: experience with Analog Devices transceivers.
• Preferred: experience with ground or airborne sensors, such as radars, EO/IR, or EW systems.
• Preferred: experience with time synchronization technologies, NTP or PTP.
• Preferred: experience with HLS synthesis and languages: C, C++, SystemC, or Chisel.
• Preferred: experience with VHDL.
• Preferred: experience designing high-speed, multi-layer digital printed circuit boards.
• Preferred: current or previous DoD security clearance.
• Preferred: experience with GPUs and/or AI engines.
• Preferred: experience with git.
• Preferred: experience with Bitbucket CI, Jenkins, or similar CI/CD flows.
• Preferred: experience with DoD and related system or software architectures and messaging standards, such as OMS, SOSA, Link-16, and others.

Conditions

Full-time, on-site at the office in Hawthorne, California.

The salary range shown is an estimate for base salary only and excludes bonus, equity, and benefits. The actual offer may vary based on, among other things, experience, education or training, critical skills, and business considerations. Applicants whose expectations fall outside the range are still welcome to apply.

Benefits

• Vision, dental, and medical plans, with premiums covered 100% by the company.
• 401k with a 50% company match up to 6% of pay, plus FSA, HSA, life insurance, and more.
• Free lunch each day, no meetings on Fridays, unlimited PTO, and a casual dress code.
• Competitive base salaries, generous pre-IPO stock option grants, and relocation assistance.
• Annual bonuses are coming soon.