Senior Wireless Engineer

Description

The company designs and manufactures high-performance unmanned systems for defense. Its systems have been tested in combat and are built at scale, and the team works quickly with hands-on engineering.

The company is building the drone capability the West needs to compete on the modern battlefield and deter its adversaries. The team wants people who act with full ownership and can get capability to warfighters within months.

You will turn the company's modem and waveform designs into deployable hardware. You will report to the Senior Wireless Systems Engineer II and work closely with the Principal Communications Systems Engineer. Your work covers getting real waveforms running on drones and working over the air.

Responsibilities

• Convert MATLAB and Simulink models of modulation, demodulation, synchronization, equalization, and channel coding or FEC into RTL in Verilog or VHDL and into embedded C
• Take floating-point models to fixed-point, weighing quantization, precision, and dynamic range trade-offs
• Write bit- and cycle-accurate testbenches that check RTL and C code against the MATLAB and Simulink golden reference
• Achieve timing closure and reduce LUT, DSP, and BRAM usage on Xilinx/AMD or Intel FPGAs and SoCs
• Split the signal chain between FPGA fabric and the embedded processor, designing the hardware and software boundary together
• Debug the physical layer using captured and live signals with the communications systems, RF, and firmware teams, and work with the Principal Communications Systems Engineer to move waveforms from model to silicon

Requirements

• Bachelor of Science in Electrical Engineering, Computer Engineering, or a related field is required. A Master's degree is highly preferred.
• 7+ years implementing DSP or communications algorithms in RTL (Verilog/VHDL) and/or embedded C for FPGA or SoC targets
• Solid DSP and digital communications fundamentals, including modulation, synchronization, equalization, filtering, and FEC/channel coding
• Hands-on fixed-point conversion and bit-true implementation from MATLAB and Simulink models
• Working knowledge of the FPGA flow in Vivado/Vitis or Quartus, covering simulation, synthesis, timing closure, and resource optimization
• Experience writing testbenches and verifying designs against a golden reference model
• Model-based design experience generating or hand-optimizing HDL and C from Simulink with MATLAB HDL Coder and Embedded Coder
• Experience implementing an end-to-end modem (OFDM, spread spectrum, or single-carrier) that shipped in hardware
• SoC integration experience with Zynq, RFSoC, or similar SoCs, including AXI interfaces and hardware/software co-design
• Familiarity with RF front ends, ADC/DAC data converters, and software-defined radio pipelines
• Hardware implementation experience with LDPC, Turbo, Viterbi, or Reed-Solomon decoders

Conditions

The US base salary range for this role is $187,000 to $261,500 USD. This is an estimate and covers base salary only. Actual pay may depend on experience, education or training, critical skills, and business considerations.

Equal opportunity employer. All applicants are welcome regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, veteran status, or disability status.

Benefits

• Highly competitive equity grants are part of the total compensation package.