Software Engineer — Computation Kernels and Performance

Description

Meet Arago and the Aragonians

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles:

Do great things: we deliver work we’re proud to sign our name to.

High velocity: speed matters. We move quickly, one step at a time.

One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

Responsibilities

• As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on Arago’s custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.
• Required Skills and Experience
• Bachelor’s, Master’s, or PhD in Computer Science, Computer Engineering, or a related field.
• Strong experience in low-level systems programming using C/C++ and assembly, with excellent understanding of how compiled software maps to machine instructions and hardware behavior.
• Deep familiarity with bare-metal development, including startup code, linker scripts, memory layout, MMIO, interrupts/exceptions, timers, synchronization, and direct peripheral access.
• Strong understanding of computer architecture, including pipelines, caches, memory hierarchies, virtual/physical addressing, atomics, DMA, and performance implications of different access patterns.
• Hands-on experience with RISC-V and/or ARM architectures, instruction sets, calling conventions, ABI concepts, and architecture-specific intrinsics.
• Experience debugging hardware/software interactions using tools such as GDB, JTAG, trace/debug interfaces, simulators, emulators, or FPGA platforms.
• Ability to read hardware specifications, register descriptions, and RTL-level documentation and translate them into robust software implementations.
• Strong performance-analysis and optimization skills, including profiling, disassembly inspection, compiler optimization behavior, and hand-tuned assembly where appropriate.
• Language: English at a proficient level. French is a plus.
• Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.
• Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.
• Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.
• Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.
• Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.
• Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.
• Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.

Conditions

Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.

Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).

Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.

Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.

Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.

Reimbursement of 50% of the public transport subscription fee.

A high-paced, multicultural (with 10 nationalities), and engineering-led environment.